SRAM memory cells that are semiconductor storage elements have a basic structure described below.
As shown in a circuit diagram in FIG. 1, the SRAM memory cell is composed of a flip flop circuit serving as an information storage section, and a pair of access transistors A1 and A2 which controls the conduction between and the flip flop circuit and data lines (bit lines BL1 and BL2) through which information is written or read. The flip flop circuit is composed of, for example, a pair of CMOS inverters each composed of one driving transistor D1 (D2) and one load transistor L1 (L2).
One of source and drain areas of the access transistor A1 (A2) is connected to a drain of the load transistor L1 (L2) and driving transistor D1 (D2). The other is connected to the bit line BL1 (BL2). Further, gates of the pair of access transistors A1 and A2 each constitute a part of a word line WL and are connected together.
A gate of the driving transistor D1 and load transistor L1 constituting one of the CMOS inverters is connected to a drain (storage node N2) of the driving transistor D2 and load transistor L2 constituting the other CMOS inverter. Further, a gate of the driving transistor D2 and load transistor L2 constituting the latter CMOS inverter is connected to a drain (storage node N1) of the driving transistor D1 and load transistor L1 constituting the former CMOS inverter. Thus, between the pair of CMOS inverters, the I/O section of one of the CMOS inverters is cross coupled to the gate of the other CMOS inverter via a pair of wires 11 and 12 called local wires.
A reference voltage (Vss, for example, GND) is supplied to a source area of each of the driving transistors D1 and D2. A power supply voltage (VDD) is supplied to a source area of each of the load transistors L1 and L2.
The above SRAM cell offers excellent element characteristics such as its resistance to noise and low power consumption during standby. However, the SRAM cell disadvantageously requires a larger cell area because of the need for six transistors for one memory cell, the need for a large number of wires, and the need for the element isolation between a p-type MOS and an n-type MOS in the same cell.
As one type of MIS type field effect transistor (hereinafter referred to as “FET”), what is called an FIN type FET has been proposed. The FIN type FET has a rectangular parallelepiped semiconductor portion that projects perpendicularly to a substrate plane and a gate electrode that strides over a top surface of the rectangular parallelepiped semiconductor portion from one side to the other side. A gate insulating film is interposed between the rectangular parallelepiped semiconductor portion and the gate electrode. A channel is formed mainly along the opposite sides of the rectangular parallelepiped semiconductor portion. Such a FIN type FET is known to be advantageous for miniaturization because the channel width can be set perpendicularly to a substrate plane. The FIN type FET is also known to be advantageous for the improvement of various characteristics such as the improvement of a cutoff characteristic and carrier mobility and the reduction of a short channel effect and punch through.
As such a FIN type FET, Patent Document 1 (Japanese Patent Laid-Open No. 64-8670) discloses a MOS field effect transistor characterized in that a semiconductor portion having a source area, a drain area, and a channel area is shaped like a rectangular parallelepiped having sides almost perpendicular to the plane of a wafer substrate, in that the height of the rectangular parallelepiped semiconductor portion is larger than its width, and in that a gate electrode extends perpendicularly to the plane of the wafer substrate.
Patent Document 1 illustrates a form in which a part of the rectangular parallelepiped semiconductor portion is a part of the silicon wafer substrate and a form in which a part of the rectangular parallelepiped semiconductor portion is a part of a single crystal silicon layer in an SOI (Silicon On Insulator) substrate. The former is shown in FIG. 2(a) and the latter is shown in FIG. 2(b).
In the form shown in FIG. 2(a), a part of a silicon wafer substrate 101 is a rectangular parallelepiped portion 103. A gate electrode 105 extends along the opposite sides of the rectangular parallelepiped portion 103 over its top. The rectangular parallelepiped portion 103 has a source area and a drain area formed opposite the respective sides of the gate electrode. A channel is formed under an insulating film 104 under the gate electrode. The channel width is equal to double the height h of the rectangular parallelepiped portion 103. The gate length corresponds to the width L of the gate electrode 105. The rectangular parallelepiped portion 103 is composed of an inner unetched part of a trench formed by anisotropically etching the silicon wafer substrate 101. The gate electrode 105 is provided on an insulating film 102 formed in the trench so as to stride over the rectangular parallelepiped portion 103.
In the form shown in FIG. 2(b), an SOI substrate is provided which comprises a silicon wafer substrate 111, an insulating layer 112, and a silicon single crystal layer. The silicon single crystal layer is patterned to form a rectangular parallelepiped portion 113. A gate electrode 115 is provided on the exposed insulating layer 112 so as to stride over the rectangular parallelepiped portion 113. The rectangular parallelepiped portion 113 has a source area and a drain area formed opposite the respective sides of a gate electrode. A channel is formed under an insulating film 114 under the gate electrode. The channel width is equal to the sum of double the height a of the rectangular parallelepiped portion 113 and the width b of the rectangular parallelepiped portion 113. The gate length corresponds to the width L of the gate electrode 115.
On the other hand, Patent Document 2 (Japanese Patent Laid-Open No. 2002-118255) discloses a FIN type FET having a plurality of rectangular parallelepiped semiconductor portions (projecting semiconductor layers 213), for example, as shown in FIGS. 3(a) to 3(c). FIG. 3(b) is a sectional view taken along line B-B in FIG. 3(a). FIG. 2(c) is a sectional view taken along line C-C in FIG. 3(a). This FIN type FET has the plurality of projecting semiconductor layers 213 composed of a part of a well layer 211 in a silicon substrate 210 and arranged parallel to one another. A gate electrode 216 is provided so as to stride over the central part of these projecting semiconductor layers. The gate electrode 216 is formed so as to extend from a top surface of an insulating film 214 along the sides of the projecting semiconductor layers 213. An insulating film 218 is interposed between the projecting semiconductor layers and the gate electrode. A channel 215 is formed in the projecting semiconductor layer under the gate electrode. Further, a source/drain area 217 is formed in each projecting semiconductor layer. A high concentration impurity layer (punch through stopper layer) is provided in an area 212 under the source/drain area 217. Upper layer wires 229 and 230 are provided via an interlayer insulating film 226 and are connected to the source/drain area 207 and the gate electrode 216, respectively, via contact plugs 228. Patent Document 2 states that this structure enables the sides of the projecting semiconductor layer to be used as the channel width, allowing the planar area to be reduced compared to conventional planar FETs.
In recent years, attempts have been made to apply these FIN type FETs to SRAMs. For example, Patent Document 3 (Japanese Patent Laid-Open No. 2-263473) describes an example in which FIN type FETs are applied to some of the transistors (having gates composed of word lines) constituting memory cells in an SRAM. Non-Patent Document 1 (Fu-Liang Yang et al, IEDM (International Electron Devices Meeting), 2003, p. 627 to 630) shows the possibility of applying FIN type FETs to an SRAM. Non-Patent Document 2 (T. Part et al, IEDM, 2003, p. 27 to 30) and Non-Patent Document 3 (Jeong-Hwan Yang et al, IEDM, 2003, p. 23 to 26) describe examples in which FIN type FETs are applied to an SRAM.